LE910Cx Hardware Design Guide
1VV0301298 Rev.40 Page 71 of 149 2023-03-16
Not Subject to NDA
HSIC Interface (Optional)
The application processor exposes a High-Speed Inter-Chip (HSIC). HSIC eliminates the
analog transceiver from a USB interface for lower voltage operation and reduced power
dissipation.
Further details will be provided in a future release of this document.
SGMII Interface
The SOC includes an integrated Ethernet MAC with an SGMII interface, with the following
key features:
This interface can be directly connected to external Ethernet devices which use
SGMII interface.
When enabled, an additional network interface will be available to the Linux
kernel.
Further details can be found at Ref 8: ETH_Expansion_board_Application Note
8.3.1. Ethernet Control interface
When using an external PHY for Ethernet connectivity, the LE910Cx also includes the
control interface for managing the external PHY
Table 27 lists the signals for controlling the external PHY
PAD Signal I/O Function Type Comment
C2 MAC_MDC O MAC to PHY
Clock
2.85V Logic Level
Specifications are
shown in Section 0,
Table 16: Operating
Range – For SD Card
Pads Operating at
2.95V
SIM Card Pads
@2.95V, Table 17
C1 MAC_MDIO I/O MAC to PHY Data 2.85V
D1 ETH_RST_N O Reset to Ethernet
PHY
2.85V
G4 ETH_INT_N I Interrupt from
Ethernet PHY
1.8V Logic Level
Specifications are
shown in Table 12
Table 27: Ethernet Control Interface Signals
Note: The Ethernet control interface is shared with USIM2 port!
When Ethernet PHY is used, USIM2 port cannot be used (and vice
versa).
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