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TMS320C6748
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SPRS590G –JUNE 2009–REVISED JANUARY 2017
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-
1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz,
E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface
(1) (2) (3)
NO. PARAMETER
1.3V, 1.2V, 1.1V, 1.0V
UNIT
MIN Nom MAX
READS and WRITES
1 t
d(TURNAROUND)
Turn around time (TA)*E - 3 (TA)*E (TA)*E + 3 ns
READS
3 t
c(EMRCYCLE)
EMIF read cycle time (EW = 0) (RS+RST+RH)*E - 3 (RS+RST+RH)*E (RS+RST+RH)*E + 3 ns
EMIF read cycle time (EW = 1) (RS+RST+RH+EWC)*E - 3 (RS+RST+RH+EWC)*E (RS+RST+RH+EWC)*E + 3 ns
4 t
su(EMCEL-EMOEL)
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0) (RS)*E-3 (RS)*E (RS)*E+3 ns
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1) -3 0 +3 ns
5 t
h(EMOEH-EMCEH)
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0) (RH)*E - 3 (RH)*E (RH)*E + 3 ns
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1) -3 0 +3 ns
6 t
su(EMBAV-EMOEL)
Output setup time, EMA_BA[1:0] valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns
7 t
h(EMOEH-EMBAIV)
Output hold time, EMA_OE high to EMA_BA[1:0] invalid (RH)*E-3 (RH)*E (RH)*E+3 ns
8 t
su(EMBAV-EMOEL)
Output setup time, EMA_A[13:0] valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns
9 t
h(EMOEH-EMAIV)
Output hold time, EMA_OE high to EMA_A[13:0] invalid (RH)*E-3 (RH)*E (RH)*E+3 ns
10 t
w(EMOEL)
EMA_OE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns
EMA_OE active low width (EW = 1) (RST+EWC)*E-3 (RST+EWC)*E (RST+EWC)*E+3 ns
11 t
d(EMWAITH-EMOEH)
Delay time from EMA_WAIT deasserted to EMA_OE high 3E-3 4E 4E+3 ns
28 t
su(EMARW-EMOEL)
Output setup time, EMA_A_RW valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns
29 t
h(EMOEH-EMARW)
Output hold time, EMA_OE high to EMA_A_RW invalid (RH)*E-3 (RH)*E (RH)*E+3 ns
WRITES
15 t
c(EMWCYCLE)
EMIF write cycle time (EW = 0) (WS+WST+WH)*E-3 (WS+WST+WH)*E (WS+WST+WH)*E+3 ns
EMIF write cycle time (EW = 1) (WS+WST+WH+EWC)*E - 3 (WS+WST+WH+EWC)*E
(WS+WST+WH+EWC)*E +
3
ns
16 t
su(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0) (WS)*E - 3 (WS)*E (WS)*E + 3 ns
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1) -3 0 +3 ns
17 t
h(EMWEH-EMCEH)
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0) (WH)*E-3 (WH)*E (WH)*E+3 ns
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1) -3 0 +3 ns
18 t
su(EMDQMV-EMWEL)
Output setup time, EMA_BA[1:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns
19 t
h(EMWEH-EMDQMIV)
Output hold time, EMA_WE high to EMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
20 t
su(EMBAV-EMWEL)
Output setup time, EMA_BA[1:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns
21 t
h(EMWEH-EMBAIV)
Output hold time, EMA_WE high to EMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns
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