Texas Instruments TMS320C6748 - Page 125

A1
A1
DDR2/mDDR
Controller
DDR2/mDDR
Device
RegionshouldencompassallDDR2/mDDRcircuitryandvaries
dependingonplacement.Non-DDR2/mDDRsignalsshouldnotbe
routedontheDDRsignallayerswithintheDDR2/mDDRkeepout
region.Non-DDR2/mDDRsignalsmayberoutedintheregion
providedtheyareroutedonlayersseparatedfromDDR2/mDDR
signallayersbyagroundlayer.Nobreaksshouldbeallowedinthe
referencegroundlayersinthisregion.Inaddition,the1.8Vpower
planeshouldcovertheentirekeepoutregion.
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TMS320C6748
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Peripheral Information and Electrical SpecificationsCopyright © 2009–2017, Texas Instruments Incorporated
6.11.3.5 DDR2/mDDR Keep Out Region
The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The
DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-21. The size of this
region varies with the placement and DDR routing. Additional clearances required for the keep out region
are shown in Table 6-28.
Figure 6-21. DDR2/mDDR Keepout Region