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TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Device Comparison Copyright © 2009–2017, Texas Instruments Incorporated
Table 3-29. General Purpose Input Output Terminal Functions (continued)
SIGNAL
TYPE
(1)
PULL
(2)
POWER
GROUP
(3)
DESCRIPTION
NAME NO.
(4) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
GP8
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]
/ PRU1_R31[27]
G1 I/O CP30] C
GPIO Bank 8
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /
PRU1_R31[26]
G2 I/O CP[30] C
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /
PRU1_R31[25]
J4 I/O CP[30] C
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /
PRU1_R31[24]
G3 I/O CP[30] C
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11] F1 I/O CP[31] C
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /
PRU1_R31[7]
F2 I/O CP[31] C
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /
PRU1_R31[6]
H4 I/O CP[31] C
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /
PRU1_R31[5]
G4 I/O CP[31] C
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] / CLKS0 F3 I/O CP[6] A
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER C16 I/O CP[7] A
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS C18 I/O CP[7] A
SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3] C19 I/O CP[8] A
SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2] D18 I/O CP[8] A
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /
SATA_MP_SWITCH
E17 I/O CP[9] A
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] /
SATA_CP_DET
D16 I/O CP[9] A
GP8[0]
(4)
K17 I/O IPD B
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