6 Deployment I/O periphery
6.1 Overview
At the CPU 314-6CF03 the analog and digital in-/output channels are
together in a 2tier casing. The following components are integrated:
n Analog input
–
4xU/Ix12bit
– 1xPt100
n Analog output
– 2xU/Ix12bit
n Digital input
– 16(8)xDC24V with parametrizable counter functions
n Digital output
– 0(8)xDC24V 1A
n Counter
– max. 4 counter with the operating mode endless, single or
periodic count
If there is no hardware configuration available, the in- and output
areas starting with address 1024 are mapped to the address range of
the CPU. In the following these areas are more described. Otherwise
the project engineering takes place after installing the
SPEEDBUS.GSD in the Siemens SIMA
TIC Manager.
The counters used here are endless counter, where the control hap-
pens via the digital input channels. For the counter you may configure
interrupts via hardware configuration that may influence the corre-
sponding digital output channel.
General
Project engineering
Counter
VIPA System 300S Deployment I/O periphery
Overview
HB140 | CPU | 314-6CF03 | GB | 16-43 129
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