For each counter the following inputs are available:
n Counter
x
(A)
–
Pulse input for counter signal respectively track A of an
encoder. Here you may connect encoder with 1-, 2- or 4-tier
evaluation.
n Counter
x
(B)
– Direction signal respectively track B of the encoder. Via the
parametrization you may invert the direction signal.
The following inputs may be assigned to a pin at the module via para-
metrization:
n Gate
x
–
This input allows you to open the HW gate with a high peek
and thus start a count process.
n Latch
x
– With a positive edge at Latch
x
the current counter value is
stored in a memory that you may read if needed.
n Reset
x
– As long as Reset
x
is applied with a positive level the counter is
still reset to the load value.
Every counter has an assigned output channel.
Ä
‘Record set 0 -
Counter mode’ on page 153
The following behavior for the output channel can be set via paramet-
rization:
n No comparison: output is not controlled
n Counter value ³ comparison value: output is set
n Counter value £ comparison value: output is set
n Counter value = comparison value: output is set
The maximum count frequency is 100kHz, independent from the
number of activated counters.
6.9
Counter - In-/output area
n By including the SPEEDBUS.GSD in your hardware configurator
,
the module is at your disposal in the hardware catalog. After the
installation of the GSD you will find the CPU at
‘Additional field devices è I/O è VIPA_SpeedBus’. 314-6CF03.
n If there is no hardware configuration available, the in- and output
areas starting with address 1024 are mapped to the address
range of the CPU.
n For each input bit the status is stored in the data input area.
n For the output you have to enter a value into the data output are.
Counter outputs
Maximum count fre-
quency
Access to the digital
part
VIPA System 300S Deployment I/O periphery
Counter - In-/output area
HB140 | CPU | 314-6CF03 | GB | 16-43 149
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