n During the count process the counter signal is recognized and
evaluated.
n Every counter occupies one double word in the input address area
with the counter register and in the input and output area one
word for the status.
By including the SPEEDBUS.GSD you may pre-set all counter
parameters via a hardware configuration. Except of the parameter in
record set 0, you may change parameters during runtime by using the
SFC 55, 56, 57 and 58. For this you have to transfer the wanted
parameters via record set to the counter by using the according SFC
in the user application. Here you may define among others:
n Interrupt behavior
n Assignment I/O (Gate, Latch, Reset, OUT)
n Input filter
n Counter operating mode respectively behavior
n Start value for load value, end value and comparison value reg-
ister
Ä
Chapter 6.10 ‘Counter - Parametrization’ on page 152
The counter is controlled via the internal gate (I-gate). The I-gate is
the sum of hardware- (HW) and software-gate (SW), where the HW-
gate evaluation may be deactivated via the parametrization.
Ä
‘Gate function’ on page 165
Depending on the status setting, the counter register contains the cur-
rent counter value (input status bit 0 = 0) or the current latch value
(input status bit 0 = 1). By setting the output status bit 8 the current
latch value is transferred to the counter register in the input area. By
setting the output status bit 8, the current counter value is transferred.
Ä
Chapter 6.9 ‘Counter - In-/output area’ on page 149
Besides of the counter register in the input area you may find a status
word for every counter in the in- respectively output area. You may
monitor the status or influence the counter by setting according bits
like e.g. activate the SW gate.
Ä
‘ISTS_
X
Input status’ on page 151,
Ä
‘OSTS_
X
Output status word’
on page 151
For not all inputs are available at the same time, you may set the
input assignment for every counter via the parametrization.
Ä
‘CPU 314-6CF03: Digital part pin assignment and status indicator ’
on page 132
Pre-set respectively
parametrize counter
Control counter
Read counter
Counter status word
Counter inputs (connec-
tions)
VIPA System 300SDeployment I/O periphery
Counter - Fast introduction
HB140 | CPU | 314-6CF03 | GB | 16-43 148
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