Xilinx ML505 User Manual

ML505/ML506/ML507 Evaluation Platform www.xilinx.com 45
UG347 (v3.1.1) October 7, 2009
Detailed Description
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Table 1-27: Configuration for SFP Module Control and Status Signals
SFP Control/Status Signal Board Connection
SFP TX FAULT
Test Point TP20
• High = Fault
• Low = Normal Operation
SFP TX DISABLE
Jumper J82
• Jumper Off = SFP Enabled
• Jumper On = SFP Disabled
SFP MOD DETECT
Test Point TP21
• High = Module Not Present
• Low = Module Present
SFP RT SEL
Jumper J81
• Jumper Off = Full Bandwidth
• Jumper On = Reduced Bandwidth
SFP LOS
Test Point TP22
• High = Loss of Receiver Signal
• Low = Normal Operation
LED DS40
• LED Off = Loss of Receiver Signal
• LED On = Normal Operation
Table 1-28: SFP Module Connections
SFP Signal FPGA Pin (U1) Description
CLKBUF_Q0_P H4
AC-coupled, LVDS, GTP REFCLK pair.
CLKBUF_Q0_N H3
SFP_RX_P G1 Receive pair.
• ML505/ML506: GTP0 of GTP_X0Y4
• ML507: GTX0 of
GTX_X0Y5
SFP_RX_N
H1
SFP_TX_P F2 Transmit pair.
• ML505/ML506: GTP0 of GTP_X0Y4
• ML507: GTX0 of
GTX_X0Y5
SFP_TX_N
G2
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Xilinx ML505 Specifications

General

Brand	Xilinx
Model	ML505
Category	Motherboard
Language	English