Xilinx VCU118

VCU118 Board User Guide 117
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD LVDS [get_ports "CLK_125MHZ_N"];
set_property PACKAGE_PIN AL20 [get_ports "FPGA_EMCCLK"];
set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_EMCCLK"];
set_property PACKAGE_PIN R32 [get_ports "USER_SMA_CLOCK_P"];
set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_P"];
set_property PACKAGE_PIN P32 [get_ports "USER_SMA_CLOCK_N"];
set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_N"];
set_property PACKAGE_PIN E12 [get_ports "250MHZ_CLK1_P"];
set_property IOSTANDARD LVDS [get_ports "250MHZ_CLK1_P"];
set_property PACKAGE_PIN D12 [get_ports "250MHZ_CLK1_N"];
set_property IOSTANDARD LVDS [get_ports "250MHZ_CLK1_N"];
set_property PACKAGE_PIN AW26 [get_ports "250MHZ_CLK2_P"];
set_property IOSTANDARD LVDS [get_ports "250MHZ_CLK2_P"];
set_property PACKAGE_PIN AW27 [get_ports "250MHZ_CLK2_N"];
set_property IOSTANDARD LVDS [get_ports "250MHZ_CLK2_N"];
set_property PACKAGE_PIN AM23 [get_ports "QSFP1_RECCLK_P"];
set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_P"];
set_property PACKAGE_PIN AM22 [get_ports "QSFP1_RECCLK_N"];
set_property IOSTANDARD LVDS [get_ports "QSFP1_RECCLK_N"];
set_property PACKAGE_PIN AP23 [get_ports "QSFP2_RECCLK_P"];
set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_P"];
set_property PACKAGE_PIN AP22 [get_ports "QSFP2_RECCLK_N"];
set_property IOSTANDARD LVDS [get_ports "QSFP2_RECCLK_N"];
set_property PACKAGE_PIN H32 [get_ports "USER_SI570_CLOCK_P "];
set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK_P"];
set_property PACKAGE_PIN G32 [get_ports "USER_SI570_CLOCK_N "];
set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK_N"];
set_property PACKAGE_PIN AW23 [get_ports "USER_SI570_CLOCK1_P"];
set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_P"];
set_property PACKAGE_PIN AW22 [get_ports "USER_SI570_CLOCK1_N"];
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