Name: Xilinx VCU118
Brand: Xilinx
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VCU118 Board User Guide 118

UG1224 (v1.0) December 15, 2016

www.xilinx.com

Appendix B: Master Constraints File Listing

set_property IOSTANDARD LVDS [get_ports "USER_SI570_CLOCK1_N"];

# SI5328

set_property PACKAGE_PIN H20 [get_ports "SI5328_INT_ALM_LS"];

set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_INT_ALM_LS"];

set_property PACKAGE_PIN BC21 [get_ports "SI5328_RST_LS"];

set_property IOSTANDARD LVCMOS12 [get_ports "SI5328_RST_LS"];

# DDR4 C1

set_property PACKAGE_PIN F11 [get_ports "DDR4_C1_DQ0"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ0"];

set_property PACKAGE_PIN E11 [get_ports "DDR4_C1_DQ1"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ1"];

set_property PACKAGE_PIN F10 [get_ports "DDR4_C1_DQ2"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ2"];

set_property PACKAGE_PIN F9 [get_ports "DDR4_C1_DQ3"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ3"];

set_property PACKAGE_PIN H12 [get_ports "DDR4_C1_DQ4"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ4"];

set_property PACKAGE_PIN G12 [get_ports "DDR4_C1_DQ5"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ5"];

set_property PACKAGE_PIN E9 [get_ports "DDR4_C1_DQ6"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ6"];

set_property PACKAGE_PIN D9 [get_ports "DDR4_C1_DQ7"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ7"];

set_property PACKAGE_PIN R19 [get_ports "DDR4_C1_DQ8"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ8"];

set_property PACKAGE_PIN P19 [get_ports "DDR4_C1_DQ9"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ9"];

set_property PACKAGE_PIN M18 [get_ports "DDR4_C1_DQ10"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ10"];

set_property PACKAGE_PIN M17 [get_ports "DDR4_C1_DQ11"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ11"];

set_property PACKAGE_PIN N19 [get_ports "DDR4_C1_DQ12"];

set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ12"];

set_property PACKAGE_PIN N18 [get_ports "DDR4_C1_DQ13"];

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