Xilinx VCU118

VCU118 Board User Guide 119
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ13"];
set_property PACKAGE_PIN N17 [get_ports "DDR4_C1_DQ14"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ14"];
set_property PACKAGE_PIN M16 [get_ports "DDR4_C1_DQ15"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ15"];
set_property PACKAGE_PIN L16 [get_ports "DDR4_C1_DQ16"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ16"];
set_property PACKAGE_PIN K16 [get_ports "DDR4_C1_DQ17"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ17"];
set_property PACKAGE_PIN L18 [get_ports "DDR4_C1_DQ18"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ18"];
set_property PACKAGE_PIN K18 [get_ports "DDR4_C1_DQ19"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ19"];
set_property PACKAGE_PIN J17 [get_ports "DDR4_C1_DQ20"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ20"];
set_property PACKAGE_PIN H17 [get_ports "DDR4_C1_DQ21"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ21"];
set_property PACKAGE_PIN H19 [get_ports "DDR4_C1_DQ22"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ22"];
set_property PACKAGE_PIN H18 [get_ports "DDR4_C1_DQ23"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ23"];
set_property PACKAGE_PIN F19 [get_ports "DDR4_C1_DQ24"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ24"];
set_property PACKAGE_PIN F18 [get_ports "DDR4_C1_DQ25"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ25"];
set_property PACKAGE_PIN E19 [get_ports "DDR4_C1_DQ26"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ26"];
set_property PACKAGE_PIN E18 [get_ports "DDR4_C1_DQ27"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ27"];
set_property PACKAGE_PIN G20 [get_ports "DDR4_C1_DQ28"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ28"];
set_property PACKAGE_PIN F20 [get_ports "DDR4_C1_DQ29"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ29"];
set_property PACKAGE_PIN E17 [get_ports "DDR4_C1_DQ30"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ30"];
set_property PACKAGE_PIN D16 [get_ports "DDR4_C1_DQ31"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ31"];
set_property PACKAGE_PIN D17 [get_ports "DDR4_C1_DQ32"];
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