Xilinx VCU118

VCU118 Board User Guide 120
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ32"];
set_property PACKAGE_PIN C17 [get_ports "DDR4_C1_DQ33"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ33"];
set_property PACKAGE_PIN C19 [get_ports "DDR4_C1_DQ34"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ34"];
set_property PACKAGE_PIN C18 [get_ports "DDR4_C1_DQ35"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ35"];
set_property PACKAGE_PIN D20 [get_ports "DDR4_C1_DQ36"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ36"];
set_property PACKAGE_PIN D19 [get_ports "DDR4_C1_DQ37"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ37"];
set_property PACKAGE_PIN C20 [get_ports "DDR4_C1_DQ38"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ38"];
set_property PACKAGE_PIN B20 [get_ports "DDR4_C1_DQ39"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ39"];
set_property PACKAGE_PIN N23 [get_ports "DDR4_C1_DQ40"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ40"];
set_property PACKAGE_PIN M23 [get_ports "DDR4_C1_DQ41"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ41"];
set_property PACKAGE_PIN R21 [get_ports "DDR4_C1_DQ42"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ42"];
set_property PACKAGE_PIN P21 [get_ports "DDR4_C1_DQ43"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ43"];
set_property PACKAGE_PIN R22 [get_ports "DDR4_C1_DQ44"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ44"];
set_property PACKAGE_PIN P22 [get_ports "DDR4_C1_DQ45"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ45"];
set_property PACKAGE_PIN T23 [get_ports "DDR4_C1_DQ46"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ46"];
set_property PACKAGE_PIN R23 [get_ports "DDR4_C1_DQ47"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ47"];
set_property PACKAGE_PIN K24 [get_ports "DDR4_C1_DQ48"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ48"];
set_property PACKAGE_PIN J24 [get_ports "DDR4_C1_DQ49"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ49"];
set_property PACKAGE_PIN M21 [get_ports "DDR4_C1_DQ50"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ50"];
set_property PACKAGE_PIN L21 [get_ports "DDR4_C1_DQ51"];
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