Xilinx VCU118

VCU118 Board User Guide 121
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ51"];
set_property PACKAGE_PIN K21 [get_ports "DDR4_C1_DQ52"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ52"];
set_property PACKAGE_PIN J21 [get_ports "DDR4_C1_DQ53"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ53"];
set_property PACKAGE_PIN K22 [get_ports "DDR4_C1_DQ54"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ54"];
set_property PACKAGE_PIN J22 [get_ports "DDR4_C1_DQ55"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ55"];
set_property PACKAGE_PIN H23 [get_ports "DDR4_C1_DQ56"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ56"];
set_property PACKAGE_PIN H22 [get_ports "DDR4_C1_DQ57"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ57"];
set_property PACKAGE_PIN E23 [get_ports "DDR4_C1_DQ58"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ58"];
set_property PACKAGE_PIN E22 [get_ports "DDR4_C1_DQ59"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ59"];
set_property PACKAGE_PIN F21 [get_ports "DDR4_C1_DQ60"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ60"];
set_property PACKAGE_PIN E21 [get_ports "DDR4_C1_DQ61"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ61"];
set_property PACKAGE_PIN F24 [get_ports "DDR4_C1_DQ62"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ62"];
set_property PACKAGE_PIN F23 [get_ports "DDR4_C1_DQ63"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ63"];
set_property PACKAGE_PIN A24 [get_ports "DDR4_C1_DQ64"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ64"];
set_property PACKAGE_PIN A23 [get_ports "DDR4_C1_DQ65"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ65"];
set_property PACKAGE_PIN C24 [get_ports "DDR4_C1_DQ66"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ66"];
set_property PACKAGE_PIN C23 [get_ports "DDR4_C1_DQ67"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ67"];
set_property PACKAGE_PIN B23 [get_ports "DDR4_C1_DQ68"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ68"];
set_property PACKAGE_PIN B22 [get_ports "DDR4_C1_DQ69"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ69"];
set_property PACKAGE_PIN B21 [get_ports "DDR4_C1_DQ70"];
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