Xilinx VCU118

VCU118 Board User Guide 122
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ70"];
set_property PACKAGE_PIN A21 [get_ports "DDR4_C1_DQ71"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ71"];
set_property PACKAGE_PIN D7 [get_ports "DDR4_C1_DQ72"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ72"];
set_property PACKAGE_PIN C7 [get_ports "DDR4_C1_DQ73"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ73"];
set_property PACKAGE_PIN B8 [get_ports "DDR4_C1_DQ74"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ74"];
set_property PACKAGE_PIN B7 [get_ports "DDR4_C1_DQ75"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ75"];
set_property PACKAGE_PIN C10 [get_ports "DDR4_C1_DQ76"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ76"];
set_property PACKAGE_PIN B10 [get_ports "DDR4_C1_DQ77"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ77"];
set_property PACKAGE_PIN B11 [get_ports "DDR4_C1_DQ78"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ78"];
set_property PACKAGE_PIN A11 [get_ports "DDR4_C1_DQ79"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DQ79"];
set_property PACKAGE_PIN D14 [get_ports "DDR4_C1_A0 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A0 "];
set_property PACKAGE_PIN B15 [get_ports "DDR4_C1_A1 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A1 "];
set_property PACKAGE_PIN B16 [get_ports "DDR4_C1_A2 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A2 "];
set_property PACKAGE_PIN C14 [get_ports "DDR4_C1_A3 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A3 "];
set_property PACKAGE_PIN C15 [get_ports "DDR4_C1_A4 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A4 "];
set_property PACKAGE_PIN A13 [get_ports "DDR4_C1_A5 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A5 "];
set_property PACKAGE_PIN A14 [get_ports "DDR4_C1_A6 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A6 "];
set_property PACKAGE_PIN A15 [get_ports "DDR4_C1_A7 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A7 "];
set_property PACKAGE_PIN A16 [get_ports "DDR4_C1_A8 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A8 "];
set_property PACKAGE_PIN B12 [get_ports "DDR4_C1_A9 "];
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