Xilinx VCU118

VCU118 Board User Guide 123
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A9 "];
set_property PACKAGE_PIN C12 [get_ports "DDR4_C1_A10"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A10"];
set_property PACKAGE_PIN B13 [get_ports "DDR4_C1_A11"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A11"];
set_property PACKAGE_PIN C13 [get_ports "DDR4_C1_A12"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A12"];
set_property PACKAGE_PIN D15 [get_ports "DDR4_C1_A13"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A13"];
set_property PACKAGE_PIN H14 [get_ports "DDR4_C1_A14_WE_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A14_WE_B"];
set_property PACKAGE_PIN H15 [get_ports "DDR4_C1_A15_CAS_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A15_CAS_B"];
set_property PACKAGE_PIN F15 [get_ports "DDR4_C1_A16_RAS_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_A16_RAS_B"];
set_property PACKAGE_PIN G15 [get_ports "DDR4_C1_BA0"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_BA0"];
set_property PACKAGE_PIN G13 [get_ports "DDR4_C1_BA1"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_BA1"];
set_property PACKAGE_PIN H13 [get_ports "DDR4_C1_BG0"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_BG0"];
set_property PACKAGE_PIN G11 [get_ports "DDR4_C1_DM0"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM0"];
set_property PACKAGE_PIN R18 [get_ports "DDR4_C1_DM1"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM1"];
set_property PACKAGE_PIN K17 [get_ports "DDR4_C1_DM2"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM2"];
set_property PACKAGE_PIN G18 [get_ports "DDR4_C1_DM3"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM3"];
set_property PACKAGE_PIN B18 [get_ports "DDR4_C1_DM4"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM4"];
set_property PACKAGE_PIN P20 [get_ports "DDR4_C1_DM5"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM5"];
set_property PACKAGE_PIN L23 [get_ports "DDR4_C1_DM6"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM6"];
set_property PACKAGE_PIN G22 [get_ports "DDR4_C1_DM7"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM7"];
set_property PACKAGE_PIN E24 [get_ports "DDR4_C1_DM8"];
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