Xilinx VCU118

VCU118 Board User Guide 124
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM8"];
set_property PACKAGE_PIN C9 [get_ports "DDR4_C1_DM9"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C1_DM9"];
set_property PACKAGE_PIN D10 [get_ports "DDR4_C1_DQS0_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS0_C"];
set_property PACKAGE_PIN D11 [get_ports "DDR4_C1_DQS0_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS0_T"];
set_property PACKAGE_PIN P16 [get_ports "DDR4_C1_DQS1_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS1_C"];
set_property PACKAGE_PIN P17 [get_ports "DDR4_C1_DQS1_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS1_T"];
set_property PACKAGE_PIN J19 [get_ports "DDR4_C1_DQS2_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS2_C"];
set_property PACKAGE_PIN K19 [get_ports "DDR4_C1_DQS2_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS2_T"];
set_property PACKAGE_PIN E16 [get_ports "DDR4_C1_DQS3_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS3_C"];
set_property PACKAGE_PIN F16 [get_ports "DDR4_C1_DQS3_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS3_T"];
set_property PACKAGE_PIN A18 [get_ports "DDR4_C1_DQS4_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS4_C"];
set_property PACKAGE_PIN A19 [get_ports "DDR4_C1_DQS4_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS4_T"];
set_property PACKAGE_PIN M22 [get_ports "DDR4_C1_DQS5_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS5_C"];
set_property PACKAGE_PIN N22 [get_ports "DDR4_C1_DQS5_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS5_T"];
set_property PACKAGE_PIN L20 [get_ports "DDR4_C1_DQS6_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS6_C"];
set_property PACKAGE_PIN M20 [get_ports "DDR4_C1_DQS6_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS6_T"];
set_property PACKAGE_PIN G23 [get_ports "DDR4_C1_DQS7_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS7_C"];
set_property PACKAGE_PIN H24 [get_ports "DDR4_C1_DQS7_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS7_T"];
set_property PACKAGE_PIN C22 [get_ports "DDR4_C1_DQS8_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS8_C"];
set_property PACKAGE_PIN D22 [get_ports "DDR4_C1_DQS8_T"];
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