Xilinx VCU118 User Manual

VCU118 Board User Guide 125
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS8_T"];
set_property PACKAGE_PIN A8 [get_ports "DDR4_C1_DQS9_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS9_C"];
set_property PACKAGE_PIN A9 [get_ports "DDR4_C1_DQS9_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C1_DQS9_T"];
set_property PACKAGE_PIN F14 [get_ports "DDR4_C1_CK_T"];
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "DDR4_C1_CK_T"];
set_property PACKAGE_PIN E14 [get_ports "DDR4_C1_CK_C"];
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "DDR4_C1_CK_C"];
set_property PACKAGE_PIN A10 [get_ports "DDR4_C1_CKE"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_CKE"];
set_property PACKAGE_PIN E13 [get_ports "DDR4_C1_ACT_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_ACT_B"];
set_property PACKAGE_PIN R17 [get_ports "DDR4_C1_ALERT_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_ALERT_B"];
set_property PACKAGE_PIN C8 [get_ports "DDR4_C1_ODT"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_ODT"];
set_property PACKAGE_PIN G10 [get_ports "DDR4_C1_PAR"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_PAR"];
set_property PACKAGE_PIN A20 [get_ports "DDR4_C1_TEN"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_TEN"];
set_property PACKAGE_PIN F13 [get_ports "DDR4_C1_CS_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C1_CS_B"];
set_property PACKAGE_PIN N20 [get_ports "DDR4_C1_RESET_B"];
set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C1_RESET_B"];
#DDR4 C2
set_property PACKAGE_PIN BD30 [get_ports "DDR4_C2_DQ0"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ0"];
set_property PACKAGE_PIN BE30 [get_ports "DDR4_C2_DQ1"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ1"];
set_property PACKAGE_PIN BD32 [get_ports "DDR4_C2_DQ2"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ2"];
set_property PACKAGE_PIN BE33 [get_ports "DDR4_C2_DQ3"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ3"];
set_property PACKAGE_PIN BC33 [get_ports "DDR4_C2_DQ4"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ4"];
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English