Xilinx VCU118

VCU118 Board User Guide 126
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN BD33 [get_ports "DDR4_C2_DQ5"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ5"];
set_property PACKAGE_PIN BC31 [get_ports "DDR4_C2_DQ6"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ6"];
set_property PACKAGE_PIN BD31 [get_ports "DDR4_C2_DQ7"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ7"];
set_property PACKAGE_PIN BA32 [get_ports "DDR4_C2_DQ8"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ8"];
set_property PACKAGE_PIN BB33 [get_ports "DDR4_C2_DQ9"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ9"];
set_property PACKAGE_PIN BA30 [get_ports "DDR4_C2_DQ10"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ10"];
set_property PACKAGE_PIN BA31 [get_ports "DDR4_C2_DQ11"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ11"];
set_property PACKAGE_PIN AW31 [get_ports "DDR4_C2_DQ12"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ12"];
set_property PACKAGE_PIN AW32 [get_ports "DDR4_C2_DQ13"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ13"];
set_property PACKAGE_PIN AY32 [get_ports "DDR4_C2_DQ14"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ14"];
set_property PACKAGE_PIN AY33 [get_ports "DDR4_C2_DQ15"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ15"];
set_property PACKAGE_PIN AV30 [get_ports "DDR4_C2_DQ16"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ16"];
set_property PACKAGE_PIN AW30 [get_ports "DDR4_C2_DQ17"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ17"];
set_property PACKAGE_PIN AU33 [get_ports "DDR4_C2_DQ18"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ18"];
set_property PACKAGE_PIN AU34 [get_ports "DDR4_C2_DQ19"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ19"];
set_property PACKAGE_PIN AT31 [get_ports "DDR4_C2_DQ20"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ20"];
set_property PACKAGE_PIN AU32 [get_ports "DDR4_C2_DQ21"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ21"];
set_property PACKAGE_PIN AU31 [get_ports "DDR4_C2_DQ22"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ22"];
set_property PACKAGE_PIN AV31 [get_ports "DDR4_C2_DQ23"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ23"];
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