Xilinx VCU118 User Manual

VCU118 Board User Guide 127
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN AR33 [get_ports "DDR4_C2_DQ24"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ24"];
set_property PACKAGE_PIN AT34 [get_ports "DDR4_C2_DQ25"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ25"];
set_property PACKAGE_PIN AT29 [get_ports "DDR4_C2_DQ26"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ26"];
set_property PACKAGE_PIN AT30 [get_ports "DDR4_C2_DQ27"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ27"];
set_property PACKAGE_PIN AP30 [get_ports "DDR4_C2_DQ28"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ28"];
set_property PACKAGE_PIN AR30 [get_ports "DDR4_C2_DQ29"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ29"];
set_property PACKAGE_PIN AN30 [get_ports "DDR4_C2_DQ30"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ30"];
set_property PACKAGE_PIN AN31 [get_ports "DDR4_C2_DQ31"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ31"];
set_property PACKAGE_PIN BE34 [get_ports "DDR4_C2_DQ32"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ32"];
set_property PACKAGE_PIN BF34 [get_ports "DDR4_C2_DQ33"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ33"];
set_property PACKAGE_PIN BC35 [get_ports "DDR4_C2_DQ34"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ34"];
set_property PACKAGE_PIN BC36 [get_ports "DDR4_C2_DQ35"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ35"];
set_property PACKAGE_PIN BD36 [get_ports "DDR4_C2_DQ36"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ36"];
set_property PACKAGE_PIN BE37 [get_ports "DDR4_C2_DQ37"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ37"];
set_property PACKAGE_PIN BF36 [get_ports "DDR4_C2_DQ38"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ38"];
set_property PACKAGE_PIN BF37 [get_ports "DDR4_C2_DQ39"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ39"];
set_property PACKAGE_PIN BD37 [get_ports "DDR4_C2_DQ40"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ40"];
set_property PACKAGE_PIN BE38 [get_ports "DDR4_C2_DQ41"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ41"];
set_property PACKAGE_PIN BC39 [get_ports "DDR4_C2_DQ42"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ42"];
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English