Xilinx VCU118 User Manual

VCU118 Board User Guide 128
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN BD40 [get_ports "DDR4_C2_DQ43"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ43"];
set_property PACKAGE_PIN BB38 [get_ports "DDR4_C2_DQ44"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ44"];
set_property PACKAGE_PIN BB39 [get_ports "DDR4_C2_DQ45"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ45"];
set_property PACKAGE_PIN BC38 [get_ports "DDR4_C2_DQ46"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ46"];
set_property PACKAGE_PIN BD38 [get_ports "DDR4_C2_DQ47"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ47"];
set_property PACKAGE_PIN BB36 [get_ports "DDR4_C2_DQ48"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ48"];
set_property PACKAGE_PIN BB37 [get_ports "DDR4_C2_DQ49"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ49"];
set_property PACKAGE_PIN BA39 [get_ports "DDR4_C2_DQ50"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ50"];
set_property PACKAGE_PIN BA40 [get_ports "DDR4_C2_DQ51"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ51"];
set_property PACKAGE_PIN AW40 [get_ports "DDR4_C2_DQ52"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ52"];
set_property PACKAGE_PIN AY40 [get_ports "DDR4_C2_DQ53"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ53"];
set_property PACKAGE_PIN AY38 [get_ports "DDR4_C2_DQ54"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ54"];
set_property PACKAGE_PIN AY39 [get_ports "DDR4_C2_DQ55"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ55"];
set_property PACKAGE_PIN AW35 [get_ports "DDR4_C2_DQ56"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ56"];
set_property PACKAGE_PIN AW36 [get_ports "DDR4_C2_DQ57"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ57"];
set_property PACKAGE_PIN AU40 [get_ports "DDR4_C2_DQ58"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ58"];
set_property PACKAGE_PIN AV40 [get_ports "DDR4_C2_DQ59"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ59"];
set_property PACKAGE_PIN AU38 [get_ports "DDR4_C2_DQ60"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ60"];
set_property PACKAGE_PIN AU39 [get_ports "DDR4_C2_DQ61"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ61"];
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English