Xilinx VCU118 User Manual

VCU118 Board User Guide 129
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN AV38 [get_ports "DDR4_C2_DQ62"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ62"];
set_property PACKAGE_PIN AV39 [get_ports "DDR4_C2_DQ63"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ63"];
set_property PACKAGE_PIN BF26 [get_ports "DDR4_C2_DQ64"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ64"];
set_property PACKAGE_PIN BF27 [get_ports "DDR4_C2_DQ65"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ65"];
set_property PACKAGE_PIN BD28 [get_ports "DDR4_C2_DQ66"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ66"];
set_property PACKAGE_PIN BE28 [get_ports "DDR4_C2_DQ67"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ67"];
set_property PACKAGE_PIN BD27 [get_ports "DDR4_C2_DQ68"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ68"];
set_property PACKAGE_PIN BE27 [get_ports "DDR4_C2_DQ69"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ69"];
set_property PACKAGE_PIN BD25 [get_ports "DDR4_C2_DQ70"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ70"];
set_property PACKAGE_PIN BD26 [get_ports "DDR4_C2_DQ71"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ71"];
set_property PACKAGE_PIN BC25 [get_ports "DDR4_C2_DQ72"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ72"];
set_property PACKAGE_PIN BC26 [get_ports "DDR4_C2_DQ73"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ73"];
set_property PACKAGE_PIN BB28 [get_ports "DDR4_C2_DQ74"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ74"];
set_property PACKAGE_PIN BC28 [get_ports "DDR4_C2_DQ75"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ75"];
set_property PACKAGE_PIN AY27 [get_ports "DDR4_C2_DQ76"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ76"];
set_property PACKAGE_PIN AY28 [get_ports "DDR4_C2_DQ77"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ77"];
set_property PACKAGE_PIN BA27 [get_ports "DDR4_C2_DQ78"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ78"];
set_property PACKAGE_PIN BB27 [get_ports "DDR4_C2_DQ79"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DQ79"];
set_property PACKAGE_PIN AM27 [get_ports "DDR4_C2_A0 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A0 "];
Send Feedback

Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English