Xilinx VCU118

VCU118 Board User Guide 130
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN AL27 [get_ports "DDR4_C2_A1 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A1 "];
set_property PACKAGE_PIN AP26 [get_ports "DDR4_C2_A2 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A2 "];
set_property PACKAGE_PIN AP25 [get_ports "DDR4_C2_A3 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A3 "];
set_property PACKAGE_PIN AN28 [get_ports "DDR4_C2_A4 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A4 "];
set_property PACKAGE_PIN AM28 [get_ports "DDR4_C2_A5 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A5 "];
set_property PACKAGE_PIN AP28 [get_ports "DDR4_C2_A6 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A6 "];
set_property PACKAGE_PIN AP27 [get_ports "DDR4_C2_A7 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A7 "];
set_property PACKAGE_PIN AN26 [get_ports "DDR4_C2_A8 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A8 "];
set_property PACKAGE_PIN AM26 [get_ports "DDR4_C2_A9 "];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A9 "];
set_property PACKAGE_PIN AR28 [get_ports "DDR4_C2_A10"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A10"];
set_property PACKAGE_PIN AR27 [get_ports "DDR4_C2_A11"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A11"];
set_property PACKAGE_PIN AV25 [get_ports "DDR4_C2_A12"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A12"];
set_property PACKAGE_PIN AT25 [get_ports "DDR4_C2_A13"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A13"];
set_property PACKAGE_PIN AV28 [get_ports "DDR4_C2_A14_WE_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A14_WE_B"];
set_property PACKAGE_PIN AU26 [get_ports "DDR4_C2_A15_CAS_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A15_CAS_B"];
set_property PACKAGE_PIN AV26 [get_ports "DDR4_C2_A16_RAS_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_A16_RAS_B"];
set_property PACKAGE_PIN AR25 [get_ports "DDR4_C2_BA0"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_BA0"];
set_property PACKAGE_PIN AU28 [get_ports "DDR4_C2_BA1"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_BA1"];
set_property PACKAGE_PIN AU27 [get_ports "DDR4_C2_BG0"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_BG0"];
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