Xilinx VCU118

VCU118 Board User Guide 131
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN BE32 [get_ports "DDR4_C2_DM0"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM0"];
set_property PACKAGE_PIN BB31 [get_ports "DDR4_C2_DM1"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM1"];
set_property PACKAGE_PIN AV33 [get_ports "DDR4_C2_DM2"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM2"];
set_property PACKAGE_PIN AR32 [get_ports "DDR4_C2_DM3"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM3"];
set_property PACKAGE_PIN BC34 [get_ports "DDR4_C2_DM4"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM4"];
set_property PACKAGE_PIN BE40 [get_ports "DDR4_C2_DM5"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM5"];
set_property PACKAGE_PIN AY37 [get_ports "DDR4_C2_DM6"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM6"];
set_property PACKAGE_PIN AV35 [get_ports "DDR4_C2_DM7"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM7"];
set_property PACKAGE_PIN BE29 [get_ports "DDR4_C2_DM8"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM8"];
set_property PACKAGE_PIN BA29 [get_ports "DDR4_C2_DM9"];
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_C2_DM9"];
set_property PACKAGE_PIN BF31 [get_ports "DDR4_C2_DQS0_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS0_C"];
set_property PACKAGE_PIN BF30 [get_ports "DDR4_C2_DQS0_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS0_T"];
set_property PACKAGE_PIN BA34 [get_ports "DDR4_C2_DQS1_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS1_C"];
set_property PACKAGE_PIN AY34 [get_ports "DDR4_C2_DQS1_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS1_T"];
set_property PACKAGE_PIN AV29 [get_ports "DDR4_C2_DQS2_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS2_C"];
set_property PACKAGE_PIN AU29 [get_ports "DDR4_C2_DQS2_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS2_T"];
set_property PACKAGE_PIN AP32 [get_ports "DDR4_C2_DQS3_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS3_C"];
set_property PACKAGE_PIN AP31 [get_ports "DDR4_C2_DQS3_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS3_T"];
set_property PACKAGE_PIN BF35 [get_ports "DDR4_C2_DQS4_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS4_C"];
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