Xilinx VCU118

VCU118 Board User Guide 132
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN BE35 [get_ports "DDR4_C2_DQS4_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS4_T"];
set_property PACKAGE_PIN BF39 [get_ports "DDR4_C2_DQS5_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS5_C"];
set_property PACKAGE_PIN BE39 [get_ports "DDR4_C2_DQS5_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS5_T"];
set_property PACKAGE_PIN BA36 [get_ports "DDR4_C2_DQS6_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS6_C"];
set_property PACKAGE_PIN BA35 [get_ports "DDR4_C2_DQS6_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS6_T"];
set_property PACKAGE_PIN AW38 [get_ports "DDR4_C2_DQS7_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS7_C"];
set_property PACKAGE_PIN AW37 [get_ports "DDR4_C2_DQS7_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS7_T"];
set_property PACKAGE_PIN BF25 [get_ports "DDR4_C2_DQS8_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS8_C"];
set_property PACKAGE_PIN BE25 [get_ports "DDR4_C2_DQS8_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS8_T"];
set_property PACKAGE_PIN BB26 [get_ports "DDR4_C2_DQS9_C"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS9_C"];
set_property PACKAGE_PIN BA26 [get_ports "DDR4_C2_DQS9_T"];
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_C2_DQS9_T"];
set_property PACKAGE_PIN AT26 [get_ports "DDR4_C2_CK_T"];
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "DDR4_C2_CK_T"];
set_property PACKAGE_PIN AT27 [get_ports "DDR4_C2_CK_C"];
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "DDR4_C2_CK_C"];
set_property PACKAGE_PIN AW28 [get_ports "DDR4_C2_CKE"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_CKE"];
set_property PACKAGE_PIN AN25 [get_ports "DDR4_C2_ACT_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_ACT_B"];
set_property PACKAGE_PIN AR29 [get_ports "DDR4_C2_ALERT_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_ALERT_B"];
set_property PACKAGE_PIN BB29 [get_ports "DDR4_C2_ODT"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_ODT"];
set_property PACKAGE_PIN BF29 [get_ports "DDR4_C2_PAR"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_PAR"];
set_property PACKAGE_PIN AY35 [get_ports "DDR4_C2_TEN"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_TEN"];
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