Xilinx VCU118

VCU118 Board User Guide 133
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property PACKAGE_PIN AY29 [get_ports "DDR4_C2_CS_B"];
set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_C2_CS_B"];
set_property PACKAGE_PIN BD35 [get_ports "DDR4_C2_RESET_B"];
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_C2_RESET_B"];
#RLD3 C3
set_property PACKAGE_PIN H39 [get_ports "RLD3_C3_72B_DQ0"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ0"];
set_property PACKAGE_PIN H40 [get_ports "RLD3_C3_72B_DQ1"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ1"];
set_property PACKAGE_PIN G40 [get_ports "RLD3_C3_72B_DQ2"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ2"];
set_property PACKAGE_PIN F40 [get_ports "RLD3_C3_72B_DQ3"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ3"];
set_property PACKAGE_PIN H38 [get_ports "RLD3_C3_72B_DQ4"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ4"];
set_property PACKAGE_PIN G38 [get_ports "RLD3_C3_72B_DQ5"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ5"];
set_property PACKAGE_PIN K37 [get_ports "RLD3_C3_72B_DQ6"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ6"];
set_property PACKAGE_PIN J37 [get_ports "RLD3_C3_72B_DQ7"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ7"];
set_property PACKAGE_PIN F38 [get_ports "RLD3_C3_72B_DQ8"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ8"];
set_property PACKAGE_PIN J35 [get_ports "RLD3_C3_72B_DQ9"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ9"];
set_property PACKAGE_PIN H35 [get_ports "RLD3_C3_72B_DQ10"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ10"];
set_property PACKAGE_PIN J36 [get_ports "RLD3_C3_72B_DQ11"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ11"];
set_property PACKAGE_PIN H37 [get_ports "RLD3_C3_72B_DQ12"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ12"];
set_property PACKAGE_PIN H34 [get_ports "RLD3_C3_72B_DQ13"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ13"];
set_property PACKAGE_PIN G35 [get_ports "RLD3_C3_72B_DQ14"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ14"];
set_property PACKAGE_PIN F35 [get_ports "RLD3_C3_72B_DQ15"];
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