Xilinx VCU118

VCU118 Board User Guide 134
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ15"];
set_property PACKAGE_PIN F36 [get_ports "RLD3_C3_72B_DQ16"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ16"];
set_property PACKAGE_PIN G36 [get_ports "RLD3_C3_72B_DQ17"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ17"];
set_property PACKAGE_PIN E37 [get_ports "RLD3_C3_72B_DQ18"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ18"];
set_property PACKAGE_PIN E38 [get_ports "RLD3_C3_72B_DQ19"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ19"];
set_property PACKAGE_PIN C39 [get_ports "RLD3_C3_72B_DQ20"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ20"];
set_property PACKAGE_PIN B40 [get_ports "RLD3_C3_72B_DQ21"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ21"];
set_property PACKAGE_PIN A39 [get_ports "RLD3_C3_72B_DQ22"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ22"];
set_property PACKAGE_PIN A40 [get_ports "RLD3_C3_72B_DQ23"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ23"];
set_property PACKAGE_PIN D40 [get_ports "RLD3_C3_72B_DQ24"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ24"];
set_property PACKAGE_PIN C40 [get_ports "RLD3_C3_72B_DQ25"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ25"];
set_property PACKAGE_PIN B38 [get_ports "RLD3_C3_72B_DQ26"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ26"];
set_property PACKAGE_PIN D35 [get_ports "RLD3_C3_72B_DQ27"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ27"];
set_property PACKAGE_PIN C35 [get_ports "RLD3_C3_72B_DQ28"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ28"];
set_property PACKAGE_PIN D34 [get_ports "RLD3_C3_72B_DQ29"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ29"];
set_property PACKAGE_PIN C34 [get_ports "RLD3_C3_72B_DQ30"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ30"];
set_property PACKAGE_PIN B36 [get_ports "RLD3_C3_72B_DQ31"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ31"];
set_property PACKAGE_PIN B37 [get_ports "RLD3_C3_72B_DQ32"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ32"];
set_property PACKAGE_PIN B35 [get_ports "RLD3_C3_72B_DQ33"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ33"];
set_property PACKAGE_PIN A36 [get_ports "RLD3_C3_72B_DQ34"];
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