Xilinx VCU118

VCU118 Board User Guide 135
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ34"];
set_property PACKAGE_PIN A34 [get_ports "RLD3_C3_72B_DQ35"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ35"];
set_property PACKAGE_PIN T24 [get_ports "RLD3_C3_72B_DQ36"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ36"];
set_property PACKAGE_PIN R24 [get_ports "RLD3_C3_72B_DQ37"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ37"];
set_property PACKAGE_PIN R27 [get_ports "RLD3_C3_72B_DQ38"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ38"];
set_property PACKAGE_PIN P27 [get_ports "RLD3_C3_72B_DQ39"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ39"];
set_property PACKAGE_PIN P25 [get_ports "RLD3_C3_72B_DQ40"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ40"];
set_property PACKAGE_PIN N25 [get_ports "RLD3_C3_72B_DQ41"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ41"];
set_property PACKAGE_PIN P26 [get_ports "RLD3_C3_72B_DQ42"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ42"];
set_property PACKAGE_PIN N27 [get_ports "RLD3_C3_72B_DQ43"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ43"];
set_property PACKAGE_PIN P24 [get_ports "RLD3_C3_72B_DQ44"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ44"];
set_property PACKAGE_PIN M25 [get_ports "RLD3_C3_72B_DQ45"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ45"];
set_property PACKAGE_PIN L26 [get_ports "RLD3_C3_72B_DQ46"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ46"];
set_property PACKAGE_PIN L28 [get_ports "RLD3_C3_72B_DQ47"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ47"];
set_property PACKAGE_PIN K28 [get_ports "RLD3_C3_72B_DQ48"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ48"];
set_property PACKAGE_PIN L24 [get_ports "RLD3_C3_72B_DQ49"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ49"];
set_property PACKAGE_PIN L25 [get_ports "RLD3_C3_72B_DQ50"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ50"];
set_property PACKAGE_PIN K26 [get_ports "RLD3_C3_72B_DQ51"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ51"];
set_property PACKAGE_PIN J26 [get_ports "RLD3_C3_72B_DQ52"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ52"];
set_property PACKAGE_PIN K27 [get_ports "RLD3_C3_72B_DQ53"];
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