Xilinx VCU118

VCU118 Board User Guide 136
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ53"];
set_property PACKAGE_PIN H27 [get_ports "RLD3_C3_72B_DQ54"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ54"];
set_property PACKAGE_PIN G27 [get_ports "RLD3_C3_72B_DQ55"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ55"];
set_property PACKAGE_PIN F28 [get_ports "RLD3_C3_72B_DQ56"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ56"];
set_property PACKAGE_PIN E28 [get_ports "RLD3_C3_72B_DQ57"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ57"];
set_property PACKAGE_PIN H28 [get_ports "RLD3_C3_72B_DQ58"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ58"];
set_property PACKAGE_PIN G28 [get_ports "RLD3_C3_72B_DQ59"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ59"];
set_property PACKAGE_PIN E26 [get_ports "RLD3_C3_72B_DQ60"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ60"];
set_property PACKAGE_PIN E27 [get_ports "RLD3_C3_72B_DQ61"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ61"];
set_property PACKAGE_PIN G25 [get_ports "RLD3_C3_72B_DQ62"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ62"];
set_property PACKAGE_PIN B28 [get_ports "RLD3_C3_72B_DQ63"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ63"];
set_property PACKAGE_PIN A28 [get_ports "RLD3_C3_72B_DQ64"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ64"];
set_property PACKAGE_PIN C27 [get_ports "RLD3_C3_72B_DQ65"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ65"];
set_property PACKAGE_PIN B27 [get_ports "RLD3_C3_72B_DQ66"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ66"];
set_property PACKAGE_PIN B26 [get_ports "RLD3_C3_72B_DQ67"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ67"];
set_property PACKAGE_PIN A26 [get_ports "RLD3_C3_72B_DQ68"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ68"];
set_property PACKAGE_PIN D25 [get_ports "RLD3_C3_72B_DQ69"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ69"];
set_property PACKAGE_PIN D26 [get_ports "RLD3_C3_72B_DQ70"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ70"];
set_property PACKAGE_PIN C25 [get_ports "RLD3_C3_72B_DQ71"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DQ71"];
set_property PACKAGE_PIN A29 [get_ports "RLD3_C3_72B_A0"];
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