Xilinx VCU118 - Page 138

VCU118 Board User Guide 138
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A19"];
set_property PACKAGE_PIN R28 [get_ports "RLD3_C3_72B_A20"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_A20"];
set_property PACKAGE_PIN E33 [get_ports "RLD3_C3_72B_BA0"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA0"];
set_property PACKAGE_PIN F33 [get_ports "RLD3_C3_72B_BA1"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA1"];
set_property PACKAGE_PIN F30 [get_ports "RLD3_C3_72B_BA2"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA2"];
set_property PACKAGE_PIN G30 [get_ports "RLD3_C3_72B_BA3"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_BA3"];
set_property PACKAGE_PIN F39 [get_ports "RLD3_C3_72B_DM0"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM0"];
set_property PACKAGE_PIN A35 [get_ports "RLD3_C3_72B_DM1"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM1"];
set_property PACKAGE_PIN N24 [get_ports "RLD3_C3_72B_DM2"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM2"];
set_property PACKAGE_PIN B25 [get_ports "RLD3_C3_72B_DM3"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_DM3"];
set_property PACKAGE_PIN J31 [get_ports "RLD3_C3_72B_DK0_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_N"];
set_property PACKAGE_PIN K31 [get_ports "RLD3_C3_72B_DK0_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK0_P"];
set_property PACKAGE_PIN J32 [get_ports "RLD3_C3_72B_DK1_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_N"];
set_property PACKAGE_PIN K32 [get_ports "RLD3_C3_72B_DK1_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK1_P"];
set_property PACKAGE_PIN J30 [get_ports "RLD3_C3_72B_DK2_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_N"];
set_property PACKAGE_PIN J29 [get_ports "RLD3_C3_72B_DK2_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK2_P"];
set_property PACKAGE_PIN G33 [get_ports "RLD3_C3_72B_DK3_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_N"];
set_property PACKAGE_PIN H33 [get_ports "RLD3_C3_72B_DK3_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_DK3_P"];
set_property PACKAGE_PIN J40 [get_ports "RLD3_C3_72B_QK0_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_N"];
set_property PACKAGE_PIN J39 [get_ports "RLD3_C3_72B_QK0_P"];
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