Xilinx VCU118 - Page 139

VCU118 Board User Guide 139
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Appendix B: Master Constraints File Listing
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK0_P"];
set_property PACKAGE_PIN E34 [get_ports "RLD3_C3_72B_QK1_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_N"];
set_property PACKAGE_PIN F34 [get_ports "RLD3_C3_72B_QK1_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK1_P"];
set_property PACKAGE_PIN D39 [get_ports "RLD3_C3_72B_QK2_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_N"];
set_property PACKAGE_PIN E39 [get_ports "RLD3_C3_72B_QK2_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK2_P"];
set_property PACKAGE_PIN C37 [get_ports "RLD3_C3_72B_QK3_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_N"];
set_property PACKAGE_PIN D37 [get_ports "RLD3_C3_72B_QK3_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK3_P"];
set_property PACKAGE_PIN R26 [get_ports "RLD3_C3_72B_QK4_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_N"];
set_property PACKAGE_PIN T26 [get_ports "RLD3_C3_72B_QK4_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK4_P"];
set_property PACKAGE_PIN M28 [get_ports "RLD3_C3_72B_QK5_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_N"];
set_property PACKAGE_PIN M27 [get_ports "RLD3_C3_72B_QK5_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK5_P"];
set_property PACKAGE_PIN F26 [get_ports "RLD3_C3_72B_QK6_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_N"];
set_property PACKAGE_PIN G26 [get_ports "RLD3_C3_72B_QK6_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK6_P"];
set_property PACKAGE_PIN C28 [get_ports "RLD3_C3_72B_QK7_N"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_N"];
set_property PACKAGE_PIN D27 [get_ports "RLD3_C3_72B_QK7_P"];
set_property IOSTANDARD DIFF_SSTL12 [get_ports "RLD3_C3_72B_QK7_P"];
set_property PACKAGE_PIN G37 [get_ports "RLD3_C3_72B_QVLD0"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD0"];
set_property PACKAGE_PIN A38 [get_ports "RLD3_C3_72B_QVLD1"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD1"];
set_property PACKAGE_PIN J27 [get_ports "RLD3_C3_72B_QVLD2"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD2"];
set_property PACKAGE_PIN F25 [get_ports "RLD3_C3_72B_QVLD3"];
set_property IOSTANDARD SSTL12 [get_ports "RLD3_C3_72B_QVLD3"];
set_property PACKAGE_PIN H29 [get_ports "RLD3_C3_72B_CK_P"];
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