Xilinx VCU118 User Manual

VCU118 Board User Guide 32
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Chapter 3: Board Component Descriptions
A40 RLD3_C3_72B_DQ23 SSTL12 B5 DQ23 U141
D40 RLD3_C3_72B_DQ24 SSTL12 B3 DQ24 U141
C40 RLD3_C3_72B_DQ25 SSTL12 A6 DQ25 U141
B38 RLD3_C3_72B_DQ26 SSTL12 A4 DQ26 U141
D35 RLD3_C3_72B_DQ27 SSTL12 J4 DQ27 U141
C35 RLD3_C3_72B_DQ28 SSTL12 K3 DQ28 U141
D34 RLD3_C3_72B_DQ29 SSTL12 K1 DQ29 U141
C34 RLD3_C3_72B_DQ30 SSTL12 L6 DQ30 U141
B36 RLD3_C3_72B_DQ31 SSTL12 L4 DQ31 U141
B37 RLD3_C3_72B_DQ32 SSTL12 L2 DQ32 U141
B35 RLD3_C3_72B_DQ33 SSTL12 M5 DQ33 U141
A36 RLD3_C3_72B_DQ34 SSTL12 M3 DQ34 U141
A34 RLD3_C3_72B_DQ35 SSTL12 N6 DQ35 U141
F39 RLD3_C3_72B_DM0 SSTL12 B7 DM0 U141
A35 RLD3_C3_72B_DM1 SSTL12 M7 DM1 U141
J39 RLD3_C3_72B_QK0_P DIFF_SSTL12 D9 QK0 U141
J40 RLD3_C3_72B_QK0_N DIFF_SSTL12 E8 QK0_B U141
F34 RLD3_C3_72B_QK1_P DIFF_SSTL12 K9 QK1 U141
E34 RLD3_C3_72B_QK1_N DIFF_SSTL12 J8 QK1_B U141
E39 RLD3_C3_72B_QK2_P DIFF_SSTL12 D5 QK2 U141
D39 RLD3_C3_72B_QK2_N DIFF_SSTL12 E6 QK2_B U141
D37 RLD3_C3_72B_QK3_P DIFF_SSTL12 K5 QK3 U141
C37 RLD3_C3_72B_QK3_N DIFF_SSTL12 J6 QK3_B U141
G37 RLD3_C3_72B_QVLD0 SSTL12 J12 QVLD0 U141
A38 RLD3_C3_72B_QVLD1 SSTL12 J2 QVLD1 U141
T24 RLD3_C3_72B_DQ36 SSTL12 D11 DQ0 U142
R24 RLD3_C3_72B_DQ37 SSTL12 E10 DQ1 U142
R27 RLD3_C3_72B_DQ38 SSTL12 C8 DQ2 U142
P27 RLD3_C3_72B_DQ39 SSTL12 C10 DQ3 U142
P25 RLD3_C3_72B_DQ40 SSTL12 C12 DQ4 U142
N25 RLD3_C3_72B_DQ41 SSTL12 B9 DQ5 U142
P26 RLD3_C3_72B_DQ42 SSTL12 B11 DQ6 U142
N27 RLD3_C3_72B_DQ43 SSTL12 A8 DQ7 U142
P24 RLD3_C3_72B_DQ44 SSTL12 A10 DQ8 U142
Table 3-4: RLD3 Memory 72-bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont’d)
FPGA
(U1) Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English