Sub module Input address Access Assignment
DI24/DO16 136 BYTE Digital input I+0.0 ... I+0.7 (X1)
137 BYTE Digital input I+1.0 ... I+1.7 (X5)
Sub module Input address Access Assignment
Counter 816 DINT Channel 0: Counter value / Frequency value
820 DINT Channel 1: Counter value / Frequency value
824 DINT Channel 2: Counter value / Frequency value
828 DINT Channel 3: Counter value / Frequency value
Sub module Output address Access Assignment
DI24/DO16 136 BYTE Digital output Q+0.0 ... Q+0.7 (X2)
137 BYTE Digital output Q+1.0 ... Q+1.3 (X6)
Sub module Output address Access Assignment
Counter 816 DWORD reserved
820 DWORD reserved
824 DWORD reserved
828 DWORD reserved
4.3.3 Option: Addressing periphery modules
The CPU M13-CCF0000 provides an I/O area (address 0 ... 2047) and a process image
of the in- and outputs (each address default 0 ... 127). The process image stores the
signal states of the lower address (default 0 ... 127) in an additional memory area. The
size of the process image can be preset via the parameterization.
Ä
Chapter 4.7 ‘Setting
standard CPU parameters’ on page 63
The process image is updated automatically when a cycle has been completed. The
process image is divided into two parts:
n process image to the inputs (PII)
n process image to the outputs (PIQ)
VIPA System MICRO
Deployment CPU M13-CCF0000
Addressing > Option: Addressing periphery modules
HB400 | CPU | M13-CCF0000 | en | 16-47 57
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