Alinx AX7021 - Page 30

ZYNQ FPGA Development Board AX7021 User Manual
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63
SD_D1
B11
64
OTG_DATA3
F14
65
SD_D0
D8
66
OTG_DATA4
A12
67
SD_CMD
C8
68
OTG_DATA5
B14
69
GND
-
70
GND
-
71
SD_D3
B9
72
OTG_DATA6
F13
73
SD_D2
E13
74
OTG_DATA7
C13
75
-
-
76
-
-
77
FPGA_TMS
G12
78
FPGA_TCK
G11
79
FPGA_TDO
G14
80
FPGA_TDI
H13
Table 2-14-1: Pin Assignment of CON1
CON2 Pin
Singal Name
ZYNQ Pin
CON2 Pin
Singal Name
ZYNQ Pin
1
B13_L1_N
V9
2
B33_L4_N
W21
3
B13_L1_P
V10
4
B33_L4_P
W20
5
B33_L10_P
AB19
6
B33_L3_N
W22
7
B33_L10_N
AB20
8
B33_L3_P
V22
9
GND
-
10
GND
-
11
B13_L4_N
W12
12
B33_L2_N
U22
13
B13_L4_P
V12
14
B33_L2_P
T22
15
B34_L6_N
M16
16
B13_L5_N
U11
17
B34_L6_P
M15
18
B13_L5_P
U12
19
GND
-
20
GND
-
21
B13_L12_N
Y8
22
B33_IO25
U14
23
B13_IO25
U7
24
B34_IO25
R15
25
B13_L23_N
W7
26
B13_L6_P
U10
27
B13_L23_P
V7
28
B13_L6_N
U9
29
GND
-
30
GND
-
31
B13_L13_N
Y5
32
B13_L19_N
T6
33
B13_L13_P
Y6
34
B13_L19_P
R6
35
B13_L24_N
W5
36
B13_L22_P
U6
37
B13_L24_P
W6
38
B13_L22_N
U5