VCU118 Board User Guide 131
UG1224 (v1.5) March 15, 2023
AppendixE: Additional Resources and Legal Notices
Sourcegate only manufactures the latest revision, which is currently A4. To order, contact
Aries Ang, aries.ang@sourcegate.net, +65 6483 2878 for price and availability. This is a
custom cable and cannot be ordered from the Sourcegate website.
Revision History
The following table shows the revision history for this document.
Date Version Revision
03/15/2023 1.5 Updated Table 3-32. Updated Figure 1-1. Updated Quad SPI Flash Memory. Updated
User Pmod GPIO Headers.
10/17/2018 1.4 Updated the PCI Express endpoint connectivity list. Added the Electrostatic
Discharge Caution section. Updated Callout 25 in Table 2 -1. Updated SW16 in
Table 2-2. Updated Jumper J7 in Table 2-3. Added Note 1 to Table 2-4. Updated the
switch positions in Figure 2-4. Updated the Virtex UltraScale+ XCVU9P-L2FLGA2104
Device, DDR4 Component Memory, RLD3 Component Memory, and PCI Express
Endpoint Connectivity descriptions. Updated the callout locations in the User I/O and
CPU Reset Pushbutton sections. Updated the 4-pole DIP SW12 devices in Table 3-29.
Revised Note 1 in Tab le 3-33. Updated the switch positions in Figure 3-30.
In Appendix B, updated the Overview and deleted the VCU118 Board Constraints File
Listing section. Updated Appendix D, Regulatory and Compliance Information.
5/09/2018 1.3 Added new information below Figure 2-4 and Table 3-25. Revised Table 3-24 notes.
Updated Figure 3-18 and Table 3-27. Updated VCU118 Board Constraints File listing.
11/10/2017 1.2 Revised binary format for PMBus INA226AIDGS power monitor in Table 3-27.
10/31/2017 1.1 Updated Figure 1-1. Revised Board Features, Board Component Location, and FPGA
Configuration. Added Quad SPI Flash Memory and Finding Additional
Documentation. Revised Appendix B, Master Constraints File Listing. Reorganized
appendices to include a new Appendix C, BPI Flash Memory for VCU118 Boards Prior
to Revision 2.0.
10/15/2016 1.0 Initial Xilinx release.
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