82
Integrated Circuit Diagrams
TMS320D707RFP/S DSP Block Diagram
78
EM_A[7]
109
1
108
72
2
107
3 106
4 105
5 104
6
103
7
102
8
101
9 100
10
99
11 98
12 97
13 96
14 95
15 94
16 93
17
92
18 91
19 90
20 89
21 88
22 87
23 86
24 85
25
84
26
83
27
82
28
81
29 80
30 79
31
32
77
33 76
34 75
35 74
36
73
110 71
111 70
112 69
113 68
114 67
115 66
116 65
117 64
118 63
119 62
120 61
121 60
122 59
123 58
124
57
125 56
126 55
127 54
128 53
129 52
130 51
131 50
132 49
133 48
134 47
135 46
136 45
137 44
138 43
139 42
140 41
141 40
142 39
143 38
37144
V
S
S
AHCLKX0/AHCLKX2
AMUTE0
AMUTE1
AHCLKX1
V
SS
ACLKX1
CV
D
D
ACLKR1
DV
DD
AFSX1
AFSR1
V
SS
RESET
V
SS
CV
DD
CLKIN
V
S
S
TMS
CV
D
D
TRST
OSCV
S
S
OSCIN
OSCOUT
OSCV
DD
V
SS
PLLHV
TDI
TDO
V
S
S
DV
D
D
EMU[0]
CV
DD
EMU[1]
TCK
V
SS
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
V
SS
SPI0_ENA/I2C1_SDA
EM_OE
DV
DD
EM_RW
CV
DD
EM_CS[2]
V
SS
EM_RAS
EM_CS[0]
EM_BA[0]
V
SS
EM_BA[1]
EM_A[10]
DV
DD
EM_A[0]
CV
DD
EM_A[1]
EM_A[2]
V
SS
EM_A[3]
CV
DD
EM_A[4]
EM_A[5]
V
S
S
DV
DD
EM_A[6]
V
SS
CV
DD
EM_A[8]
EM_A[9]
EM_A[11]
DV
DD
V
SS
SPI0_SIMO
SPI0_SOMI/I2C0_SDA
DV
DD
AXR0[0]
V
SS
AXR0[1]
AXR0[2]
AXR0[3]
V
SS
AXR0[4]
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
CV
DD
V
SS
DV
DD
AXR0[8]/AXR1[5]/SPI1_SOMI
AXR0[9]/AXR1[4]/SPI1_SIMO
CV
DD
V
SS
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
CV
DD
V
SS
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
DV
DD
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR0
V
SS
AFSR0
ACLKX0
AHCLKR0/AHCLKR1
AFSX0
V
SS
EM_CLK
EM_CKE
V
SS
DV
DD
EM_WE_DQM[1]
EM_D[8]
CV
DD
EM_D[9]
EM_D[10]
V
SS
EM_D[11]
DV
DD
EM_D[12]
EM_D[13]
CV
DD
EM_D[14]
EM_D[15]
V
SS
CV
DD
EM_D[0]
EM_D[1]
DV
DD
EM_D[2]
EM_D[3]
V
SS
EM_D[4]
EM_D[5]
CV
DD
EM_D[6]
DV
DD
EM_D[7]
V
SS
EM_WE_DQM[0]
EM_WE
EM_CAS
Top View
Block Diagram
Program/Data
RAM
192K Bytes
192
256
Program/Data
ROM Page1
256K Bytes
256
256
256K Bytes
ROM Page3
Program/Data
Program/Data
ROM Page2
256K Bytes
3232
DMPPMP
CSP 32
256
Program
Cache
32K Bytes
64
D1
Data
R/W
R/W
Data
D2
64
256
Program
FetchINTI/O
C67x+ CPU
Memory
Controller
32
High-Performance
Crossbar Switch
32
McASP DMA Bus
JTAG EMU
32
32
32
32
32
32
32
Peripheral Configuration Bus
EMIF
32
Events
In
32
MAX1MAX0
32
CONTROL
32
Interrupts
Out
I/O
dMAX
McASP0
16 Serializers
McASP1
6 Serializers
McASP2
2 Serializers
DIT Only
SPI1
SPI0
I2C1
I2C0
RTI32
PLL
Peripheral Interrupt and DMA Events
32
32
32
32
TMS320D707RFP/S DSP Pinout Diagram