84
Integrated Circuit Diagrams
TMS320D707RFP/S DSP Pin Function Table (continued)
PIN
SIGNAL NAME TYPE
(1)
PULL
(2)
GPIO
(3)
DESCRIPTION
NO.
McASP0, McASP1, McASP2, and SPI1 Serial Ports
AHCLKR0/AHCLKR1 143 IO - Y McASP0 and McASP1 Receive Master Clock
ACLKR0 139 IO - Y McASP0 Receive Bit Clock
AFSR0 141 IO - Y McASP0 Receive Frame Sync (L/R Clock)
AHCLKX0/AHCLKX2 2 IO - Y McASP0 and McASP2 Transmit Master Clock
ACLKX0 142 IO - Y McASP0 Transmit Bit Clock
AFSX0 144 IO - Y McASP0 Transmit Frame Sync (L/R Clock)
AMUTE0 3 O - Y McASP0 MUTE Output
AXR0[0] 113 IO - Y McASP0 Serial Data 0
AXR0[1] 115 IO - Y McASP0 Serial Data 1
AXR0[2] 116 IO - Y McASP0 Serial Data 2
AXR0[3] 117 IO - Y McASP0 Serial Data 3
AXR0[4] 119 IO - Y McASP0 Serial Data 4
AXR0[5]/SPI1_SCS
120 IO - Y McASP0 Serial Data 5 or SPI1 Slave Chip Select
AXR0[6]/SPI1_ENA 121 IO - Y McASP0 Serial Data 6 or SPI1 Enable (Ready)
AXR0[7]/SPI1_CLK 122 IO - Y McASP0 Serial Data 7 or SPI1 Serial Clock
AXR0[8]/AXR1[5]/ McASP0 Serial Data 8 or McASP1 Serial Data 5 or
126 IO - Y
SPI1_SOMI SPI1 Data Pin Slave Out Master In
AXR0[9]/AXR1[4]/ McASP0 Serial Data 9 or McASP1 Serial Data 4 or
127 IO - Y
SPI1_SIMO SPI1 Data Pin Slave In Master Out
AXR0[10]/AXR1[3] 130 IO - Y McASP0 Serial Data 10 or McASP1 Serial Data 3
AXR0[11]/AXR1[2] 131 IO - Y McASP0 Serial Data 11 or McASP1 Serial Data 2
AXR0[12]/AXR1[1] 134 IO - Y McASP0 Serial Data 12 or McASP1 Serial Data 1
AXR0[13]/AXR1[0] 135 IO - Y McASP0 Serial Data 13 or McASP1 Serial Data 0
AXR0[14]/AXR2[1] 137 IO - Y McASP0 Serial Data 14 or McASP2 Serial Data 1
AXR0[15]/AXR2[0] 138 IO - Y McASP0 Serial Data 15 or McASP2 Serial Data 0
ACLKR1 9 IO - Y McASP1 Receive Bit Clock
AFSR1 12 IO - Y McASP1 Receive Frame Sync (L/R Clock)
AHCLKX1 5 IO - Y McASP1 Transmit Master Clock
ACLKX1 7 IO - Y McASP1 Transmit Bit Clock
AFSX1 11 IO - Y McASP1 Transmit Frame Sync (L/R Clock)
AMUTE1 4 O - Y McASP1 MUTE Output
SPI0, I2C0, and I2C1 Serial Port Pins
SPI0_SOMI/I2C0_SDA 111 IO - Y SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
SPI0_SIMO 110 IO - Y SPI0 Data Pin Slave In Master Out
SPI0_CLK/I2C0_SCL 108 IO - Y SPI0 Serial Clock or I2C0 Serial Clock
SPI0_SCS/I2C1_SCL 107 IO - Y SPI0 Slave Chip Select or I2C1 Serial Clock
SPI0_ENA/I2C1_SDA
105 IO - Y SPI0 Enable (Ready) or I2C1 Serial Data
Pin Functions (continued):
Clocks
OSCIN 23 I - N 1.2-V Oscillator Input
OSCOUT 24 O - N 1.2-V Oscillator Output
OSCV
DD
25 PWR - N Oscillator 1.2-V V
DD
tap point (for filter only)
OSCV
SS
22 PWR - N Oscillator V
SS
tap point (for filter only)
CLKIN 17 I - N Alternate clock input (3.3-V LVCMOS Input)
PLLHV 27 PWR - N PLL 3.3-V Supply Input (requires external filter)
Device Reset
RESET
14 I - N Device reset pin
Emulation/JTAG Port
TCK 35 I IPU N Test Clock
TMS 19 I IPU N Test Mode Select
TDI 28 I IPU N Test Data In
TDO 29 OZ IPU N Test Data Out
TRST
21 I IPD N Test Reset
EMU[0]
32 IO IPU N Emulation Pin 0
EMU[1]
34 IO IPU N Emulation Pin 1
Power Pins
Core Supply (CV
DD
) 8, 16, 20, 33, 44, 53, 57, 65, 77, 85, 90, 101, 123, 128, 132
IO Supply (DV
DD
) 10, 31, 42, 50, 60, 68, 73, 81, 92, 103, 112, 125, 136
Ground (V
SS
) 1, 6, 13, 15, 18, 26, 30, 36, 40, 47, 54, 62, 69, 72, 78, 82, 87, 95, 99, 106, 109, 114, 118, 124, 129, 133, 140
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