85
LM393 Dual Voltage Comparator
Integrated Circuit Diagrams
74HC166 8-bit Shift Register
1
2
3
45
6
7
8
+
-
+
-
1. Output1
2. Inverting input1
3. Non-inverting input
4. -Vcc
5. Non-inverting input
6. Inverting input 2
7. Output 2
8. +Vcc
Packag
S
e
chematic
Truth Table (Positive Logic)
8
1
1
2
3
45
6
7
8
N/C
_
V
CC
V
E
V
O
GND
+
N/C
V
F
6N137
tuptuO elbanE tupnI
L H H
H H L
H L H
H L L
L CN H
H CN L
6N137 Optocoupler
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
DS
D0
D1
D2
D3
CE
GND
CP
V
CC
D7
Q7
D6
D5
D4
MR
PE
Functional Diagram
TRUTH TABLE
INPUTS
INTERNAL
Q STATES
OUTPUT
Q7
MASTER
RESET
PARALLEL
ENABLE
CLOCK
ENABLE CLOCK SERIAL
PARALLEL
D0 D7 Q0 Q1
LXXXXXLLL
H X L L X X Q00 Q10 Q0
HLL? X a...h a b h
HHL ? H X H Q0n Q6n
HHL ? L X L Q0n Q6n
HXH? X X Q00 Q10 Q70
H= High Voltage Level
L= Low Voltage Level
X= Don’t Care
? = Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ? transition of the clock.
8 - REGISTERS
PARALLEL ENABLE CIRCUIT
D0 D1 D2 D3 D4 D5 D6 D7
PE
D
S
CP
CE
MR
D0 D7
Q7
Pin Descriptions
Truth Table
H HIGH Voltage Level Z High Impedance
L
LOW Voltage Level X Immaterial
Pin Assignments
Pin Names Description
A
n
Inputs
OE
n
Output Enable Inputs
O
n
Outputs
Inputs Output
OE
n
A
n
O
n
LLL
LHH
HXZ
74LCX125M CMOS Quad Bus Buffer
To Next Page
Loading...
Need help?
General