Bridgetek FT801 - Page 42

FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
42
Product Page
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Register Definition 17 REG_HCYCLE
Please reference to section 2.2.1
31 9 0
Address: 0x102428
Reset Value: 0x224
Note: NONE
REG_HCYCLE Definition
Bit0 - 9: These bits are the number of total PCLK cycles per horizontal line scan. The
default value is 548 and supposed to support 480x272 screen resolution display. Please
check the display panel specification for more details.
R/W
Reserved
Register Definition 18 REG_TAP_MASK
31 0
Address: 0x102424
Reset Value: 0xFFFFFFFF
Note: NONE
R/W
Bit0 - 31: These bits are used to mask the value of RGB output signals. The result will be used
to caculate the CRC value which will be updated into REG_TAP_CRC.
REG_TAP_MASK Definition