Bridgetek FT801 - Page 65

FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
65
Product Page
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Register Definition 48 REG_PLAYBACK_LOOP Definition
R/W
31 1 0
REG_PLAYBACK_LOOP Definition
Address: 0x1024B8
Reset Value: 0x0
Note: Please refer to the datasheet section "Audio Playback" for the details of
this register.
Reserved
Bit 0 : this bit controls the audio engine to play back the audio data in RAM_G
from the start address once it consumes all the data. A value of 1 means LOOP
is enabled, a value of 0 means LOOP is disabled.
Register Definition 49 REG_PLAYBACK_FORMAT Definition
Address: 0x1024B4
Reset Value: 0x0
Note: Please read the datasheet section "Audio Playback" for more details.
Bit 0 - 1 : These bits define the format of the audio data in RAM_G. FT800
supports:
00: Linear Sample format
01: uLaw Sample format
10: 4 bit IMA ADPCM Sample format
11: Undefined.