Bridgetek FT801 - Page 75

FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
75
Product Page
Document Feedback Copyright © Bridgetek Limited
Register Definition 64 REG_GPIO_DIR Definition
31 8 7 0
REG_GPIO_DIR Definition
Address: 0x10248C
Reset Value: 0x80
Bit 0 - 7 : These bits configure the direction of GPIO pins of the FT800. Bit 0 controls
the direction of GPIO0 and Bit 7 controls the direction of GPIO7. The bit value 1
means the GPIO pin is set as an output, otherwise it means an input. After reset, only
the GPIO7 is set to output by default.
R/W
Reserved
Register Definition 65 REG_CPURESET Definition
RW
31 1 0
Address: 0x10241C Reset Value: 0x00
Bit 1 - 31: Reserved
Bit 0: Write this bit to 1 will set the coprocessor engines of the FT800
into the reset state. Write this bit to 0 will resume from reset state to
normal operational mode. If this bit is read as 1, the FT800 coprocessor
engines are in reset state. Otherwise, FT800 corpocessor engines are in
normal state.
Reserved
REG_CPURESET Definition