4.5.5 System Initialization
When the power is turned on, a sequence of system initialization and test routines is initiated. The decoder board
is tested for the following: proper battery-backed clock operation, all hardware watchdog tests, address code plug
verification and any failures in the critical outputs. The status display shows these tests in progress, then goes on
to display extensive information about the system design, date of engineering, etc.
Note: During system initialization, if a properly identified controller comes ‘on the air’, the last portion of the
power-on display information (system design, date of engineering, etc.) will be bypassed.
After completing the power-on tests, the decoder looks for a properly addressed message from the controller.
When a message is received with a valid system address and proper BCH (Data Integrity Character), the Cattron
MP96 system decoder quickly tests the operability of the two OPR output relays.
The two OPRs (OPR1 and OPR2) are normally wired to the machine ‘STOP’ or ‘MAINLINE’ circuits. They must
turn off when there is a STOP command and/or loss of valid data from the operator’s controller. As an additional
safety feature, the two relays are used in series with the MP96.
To ensure reliable operation of these relays, the two OPRs are energized individually while the system checks for
an activity level. This helps to ensure that the equipment will be controlled safely and will shut down when
commanded. When both OPRs are energized, the Cattron MP96 system decoder is ‘on-line’, has watchdog
devices activated, and is able to output new commands as received from the operator. In addition, up to six
individual mainline contactors may be energized for separate circuits of the controlled equipment.
4.5.6 Multiple Watchdog Circuits (Hardware and Software)
The MP96 decoder has hardware and software ‘watchdog’ circuits designed to ‘shut down’ the machine when
conditions are not valid to allow continued operation. These safety circuits ultimately disconnect output function
relays, motor mainline relays and the machine mainline relays (OPR1 and OPR2).
Hardware watchdogs are electronic component timers that will turn off if they are not constantly re-activated and
reset by valid, fully decoded messages. These timers are tested for timing accuracy at power-on of the
equipment, using the microcomputer’s timer interrupt reference. The exact setting of these timers is controlled by
a potentiometer on the circuit board. The potentiometer is set according to the system’s requirements at the time
of system engineering.
Software watchdogs are similar to the hardware watchdogs, except they are timed in the control and secondary
microcomputers. They perform the same shut-down operation when valid messages stop being decoded.
Software and hardware watchdogs work together in pairs, one backing up the other (software/hardware).
All three microcomputers have software code that is written with embedded watchdog timers to ensure proper
code sequences occur.
4.5.7 Automatic Safety Override (ASO)
The Automatic Safety Override (ASO) function continually monitors all critical and directional relay outputs from
the MP96 receiver/decoder. The ASO circuit disables the OPR (shutting down the controlled machinery) if a
critical or directional output relay is active when no corresponding command is being received from the controller.
In this event, no action is required by the operator to stop the equipment. The ASO safety circuitry will stop motion
automatically without any operator command when a critical or directional output relay fault is detected.
When Cattron application engineers configure the MP96 interface to a specific machine, they determine which
relay output functions are critical to safe operation. Once identified, such critical relay outputs are continually
monitored for their ‘ON/OFF’ status.
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