Table 5-3: DMA and Audio Channel Enable Bits
DMACON REGISTER
Bit Name Function
15 SET/CLR When this bit is written as a 1, it
sets any bit in DMACONW for which
the corresponding bit position is
also a 1, leaving all other bits alone.
9 DMAEN Only while this bit is a 1 can
any direct memory access occur.
3 AUD3EN Audio channel 3 enable.
2 AUD2EN Audio channel 2 enable.
1 AUD1EN Audio channel 1 enable.
0 AUD0EN Audio channel 0 enable.
For example, if you are using channel 0, then you write a 1 into bit 9 to enable DMA and a
1 into bit 0 to enable the audio channel, as shown below.
BEGINCHAN0:
LEA CUSTOM,a0
MOVE.W #(DMAF_SETCLR!DMAF_AUD0!DMAF_MASTER),DMACON(a0)
STOPPING THE AUDIO DMA
You can stop the channel by writing a 0 into the AUDxEN bit at any time. However, you
cannot resume the output at the same point in the waveform by just writing a 1 in the bit
again. Enabling an audio channel almost always starts the data output again from the top
of the list of data pointed to by the location registers for that channel. If the channel is
disabled for a very short time (less than two sampling periods) it may stay on and thus
continue from where it left off.
The following example shows how to stop audio DMA for one channel.
STOPAUDCHAN0:
LEA CUSTOM,a0
MOVE.W #(DMAF_AUD0),DMACON(a0)
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- Audio Hardware 141 -
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