NONMASKABLE INTERRUPT
Interrupt level 7 is the non-maskable interrupt and is not generated anywhere in the
current system. The raw interrupt lines of the 68000, IPL2 through IPL0, are brought out
to the expansion connector and can be used to generate this level 7 interrupt for
debugging purposes.
MASKABLE INTERRUPTS
Interrupt levels 1 through 6 are generated. Control registers within the peripherals chip
allow you to mask certain of these sources and prevent them from generating a 68000
interrupt.
USER INTERFACE TO THE INTERRUPT SYSTEM
The system software has been designed to correctly handle all system hardware interrupts
at levels 1 through 6. A separate set of input lines, designated INT2* and INT6* 1 have
been routed to the expansion connector for use by external hardware for interrupts. These
are known as the external low- and external high-level interrupts.
These interrupt lines are connected to the peripherals chip and create interrupt levels 2
and 6, respectively. It is recommended that you take advantage of the interrupt handlers
built into the operating system by using these external interrupt lines rather than
generating interrupts directly on the processor interrupt lines.
INTERRUPT CONTROL REGISTERS
There are two interrupt registers, interrupt enable (mask) and interrupt request (status).
Each register has both a read and a write address.
The names of the interrupt addresses are;
INTENA
Interrupt enable (mask) - write only. Sets or clears specific bits of INTENA.
INTENAR
Interrupt enable (mask) read - read only. Reads contents of INTENA.
1 A * indicates an active low signal.
- 212 System Control Hardware -
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