Table 6-2: Typical Blitter Cycle Sequence
USE Code
in Active
BLTCON0 Channels Cycle Sequence
F A B C D A0 B0 C0 - A1 B1 C1 D0 A2 B2 C2 D1 D2
E A B C A0 B0 C0 A1 B1 C1 A2 B2 C2
D A B D A0 B0 - A1 B1 D0 A2 B2 D1 - D2
C A B A0 B0 - A1 B1 - A2 B2
B A C D A0 C0 - A1 C1 D0 A2 C2 D1 - D2
A A C A0 C0 A1 C1 A2 C2
9 A D A0 - A1 D0 A2 D1 - D2
8 A A0 - A1 - A2
7 B C D B0 C0 - - B1 C1 D0 - B2 C2 D1 - D2
6 B C B0 C0 - B1 C1 - B2 C2
5 B D B0 - - B1 D0 - B2 D1 - D2
4 B B0 - - B1 - - B2
3 C D C0 - - C1 D0 - C2 D1 - D2
2 C C0 - C1 - C2
1 D D0 - D1 - D2
0 none
Notes for the above Table:
o No fill.
o No competing bus activity.
o Three-word blit.
o Typical operation involves fetching all sources twice before the first destination becomes
available. This is due to internal pipelining. Care must be taken with overlapping source
and destination regions.
NOTE
This Table is only meant to be an illustration of the typical order of blitter cycles on the
bus. Bus cycles are dynamically allocated based on blitter operating mode; competing bus
activity from processor, bitplanes, and other DMA channels; and other factors.
Commodore Amiga does not guarantee the accuracy of or future adherence to this chart.
We reserve the right to make product improvements or design changes in this area
without notice.
- Blitter Hardware 183 -
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