Figure 8-5: Effects of Resistance on Charging Rate
You normally issue POTGO at the beginning of a video screen, then read the values in the
POT registers during the next vertical blanking period, just before issuing POTGO again.
Nothing in the system prevents the counters from overflowing (wrapping past a count of
255). However, the system is designed to insure that the counter cannot overflow within
the span of a single screen. This allows you to know for certain whether an overflow is
indicated by the controller.
PROPORTIONAL CONTROLLER REGISTERS
The following registers are used for the proportional controllers:
POT0DAT - port 1 data (vertical/horizontal3
POT1DAT - port 2 data (vertical/horizontal)
Bit positions:
Bits 15-8 POT0Y value or POT1Y value
Bits 7-0 POT0X value or POT1X value
All counts are reset to zero when POTGO is written with bit zero high. Counts are normally
read one frame after the scan circuitry is enabled.
- 230 Interface Hardware -
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