ZERO FLAG
A blitter zero flag is provided that can be tested to determine if the logic operation
selected has resulted in zero bits for all destination bits, even if those destination bits are
not written due to the D DMA channel being disabled. This feature is often useful for
collision detection, by performing a logical "and" on two source images to test for overlap.
If the images do not overlap, the zero flag will stay true.
The Zero flag is only valid after the blitter has completed its operation and can be read
from bit DMAF_BLTNZERO of the DMACONR register.
PIPELINE REGISTER
The blitter performs many operations in each cycle - shifting and masking source words,
logical combination of sources, and area fill and zero detect on the output. To enable so
many things to take place so quickly, the blitter is pipelined. This means that rather than
performing all of the above operations in one blitter cycle, the operations are spread over
two blitter cycles. (Here "cycle" is used very loosely for simplicity.) To clarify this, the
blitter can be imagined as two chips connected in series. Every cycle, a new set of source
operations come in, and the first chip performs its operations on the data. It then passes
the half-processed data to the second chip to be finished during the next cycle, when the
first chip will be busy at work on the next set of data. Each set of data takes two "cycles"
to get through the two chips, overlapped so a set of data can be pumped through each
cycle.
What all this means is that the first two sets of sources are fetched before the first
destination is written. This allows you to shift a bitmap up to one word to the right using
ascending mode, for instance, even though normally parts of the destination would be
overwritten before they were fetched.
- 182 Blitter Hardware -
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