o If bit 7 is a 1, then any bit 6-0 in your own mask byte which is set
to a 1 sets the corresponding bit in the MASK register. Any bit that you
have set to a 0 causes the MASK register bit to remain in its current
state.
o If bit 7 is a 0, then any bit 6-0 in your own mask byte which is set
to a 1 clears the corresponding bit in the MASK register. Again, any 0
bit in your own mask byte causes no change in the contents of the
corresponding MASK register bit.
If an interrupt is to occur based on a particular condition, then that
corresponding MASK bit must be a 1.
Example: Suppose you want to set the Timer A interrupt bit (enable the
Timer A interrupt), but want to be sure that all other interrupts are
cleared. Here is the sequence you can use:
INCLUDE "hardware/cia.i"
XREF ciaa ; From amiga.lib
lea ciaa,a0 ; Defined in amiga.lib
move.b 401111110,ciaicr(a0)
MSB is 0, means clear any bit whose value is 1 in the rest of the byte
INCLUDE "hardware/cia.i"
XREF ciaa ; From amiga.lib
lea ciaa,a0 ; Defined in amiga.lib
move.b %100000001,ciaicr(a0)
MSB is 1, means set any bit whose value is 1 in the rest of the byte (do
not change any values wherein the written value bit is a zero)
READ INTERRUPT CONTROL REGISTER
REG NAME D7 D6 D5 D4 D3 D2 D1 D0
--- ---- -- -- -- -- -- -- -- --
D ICR IR 0 0 FLG SP ALRM TB TA
WRITE INTERRUPT CONTROL MASK
REG NAME D7 D6 D5 D4 D3 D2 D1 D0
--- ---- -- -- -- -- -- -- -- --
D ICR S/C x x FLG SP ALRM TB TA
- 326 Appendix F -
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