REGISTER FUNCTIONAL DESCRIPTION
I/O PORTS (PRA, PRB, DDRA, DDRB)
Ports A and B each consist of an 8-bit peripheral data register (PR) and
an 8-bit data direction register (DDR). If a bit in the DDR is set to a
1, the corresponding bit position in the PR becomes an output. If a DDR
bit is set to a 0, the corresponding PR bit is defined as an input.
When you READ a PR register, you read the actual current state of the I/O
pins (PA0-PA7, PB0-PB7, regardless of whether you have set them to be
inputs or outputs.
Ports A and B have passive pull-up devices as well as active pull-ups,
providing both CMOS and TTL compatibility. Both ports have two TTL load
drive capability.
In addition to their normal IO operations, ports PB6 and PB7 also provide
timer output functions.
HANDSHAKING
Handshaking occurs on data transfers using the PC output pin and the FLAG
input pin. PC will go low on the third cycle after a port B access. This
signal can be used to indicate "data ready" at port B or "data accepted"
from port B. Handshaking on 16-bit data transfers (using both ports
A and B) is possible by always reading or writing port A first. FLAG is a
negative edge-sensitive input that can be used for receiving the PC
output from another 8520 or as a general purpose interrupt input. Any
negative transition on FLAG will set the FLAG interrupt bit.
REG NAME D7 D6 D5 D4 D3 D2 D1 D0
--- ---- -- -- -- -- -- -- -- --
0 PRA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
1 PRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
2 DDRA DPA7 DPA6 DPA5 DPA4 DPA3 DPA2 DPA1 DPA0
3 DDRB DPB7 DPB6 DPB5 DPB4 DPB3 DPB2 DPB1 DPB0
INTERVAL TIMERS (TIMER A, TIMER B)
Each interval timer consists of a 16-bit read-only timer counter and a
16-bit write-only timer latch. Data written to the timer is latched into
the timer latch, while data read from the timer is the present contents
of the timer counter.
- 320 Appendix F -
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