BLITTER OPERATIONS AND SYSTEM DMA
The operations of the blitter affect the performance of the rest of the system. the
following sections explain how system performance is affected by blitter direct memory
access priority, DMA time slot allocation, bus sharing between the 68000 and the display
hardware, the operations of the blitter and Copper, and different playfield display sizes.
The blitter performs its various data-fetch, modify, and store operations through DMA
sequences, and it shares memory access with other devices in the, system. Each device
that accesses memory has a priority level assigned to it, which indicates its importance
relative to other devices.
Disk DMA, audio DMA, display DMA, and sprite DMA all have the highest priority level.
Display DMA has priority over sprite DMA under certain circumstances. Each of these four
devices is allocated a group of time slots during each horizontal scan of the video beam. If
a device does not request one of its allocated time slots, the slot is open for other uses.
These devices are given first priority because missed DMA cycles can cause lost data,
noise in the sound output, or on-screen interruptions.
The Copper has the next priority because it has to perform its operations at the same time
during each display frame to remain synchronized with the display beam sweeping across
the screen.
The lowest priorities are assigned to the blitter and the 68000, in that order. The blitter is
given the higher priority because it performs data copying, modifying, and line drawing
operations operations much faster than the 68000.
During a horizontal scan line (about 63 microseconds), there are 227.5 "color clocks", or
memory access cycles. A memory cycle is approximately 280ns in duration. The total of
227.5 cycles per horizontal line includes both display time and non-display time. Of this
total time, 226 cycles are available to be allocated to the various devices that need
memory access.
The time-slot allocation per horizontal line is
4 cycles for memory refresh
3 cycles for disk DMA
4 cycles for audio DMA (2 bytes per channel)
16 cycles for sprite DMA (2 words per channel)
80 cycles for bit-plane DMA (even or odd numbered slots according to the display size
used)
Figure 6-9 shows one complete horizontal scan line and how the clock cycles are
allocated.
- Blitter Hardware 189 -
To Next Page
Loading...
