The latch is also called a prescalar in that it represents the countdown
value which must be counted before the timer reaches an underflow (no
more counts) condition. This latch (prescalar) value is a divider of the
input clocking frequency. The timers can be used independently or linked
for extended operations. Various timer operating modes allow generation
of long time delays, variable width pulses, pulse trains, and variable
frequency waveforms. Utilizing the CNT input, the timers can count
external pulses or measure frequency, pulse width, and delay times of
external signals.
Each timer has an associated control register, providing independent
control over each of the following functions:
START/STOP
A control bit allows the timer to be started or stopped by the
microprocessor at any time.
PB ON/OFF
A control bit allows the timer output to appear on a port B output line
(PB6 for timer A and PB7 for timer B). This function overrides the DDRB
control bit and forces the appropriate PB line to become an output.
TOGGLE/PULSE
A control bit selects the output applied to port B while the PB on/off
bit is ON. On every timer underflow, the output can either toggle or
generate a single positive pulse of one cycle duration.
The toggle output is set high whenever the timer is started, and set low
by RES.
ONE-SHOT/CONTINUOUS
A control bit selects either timer mode. In one-shot mode, the timer will
count down from the latched value to zero, generate an interrupt, reload
the latched value, then stop. In continuous mode, the timer will count
down from the latched value to zero, generate an interrupt, reload the
latched value, and repeat the procedure continuously.
In one-shot mode, a write to timer-high (register 5 for timer A, register
7 for Timer B) will transfer the timer latch to the counter and initiate
counting regardless of the start bit.
- Appendix F 321 -
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